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Weltrend Semiconductor, Inc.
WT6148/WT6160
Digital Monitor Controller
(ROM Type)
Preliminary Data Sheet
REV. 1.02 Sep. 4, 02
The information in this document is subject to change without notice. (c) Weltrend Semiconductor, Inc. All Rights Reserved.
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2F, No. 24, Industry E. 9th RD., Science-Based Industrial Park, Hsin-Chu, Taiwan TEL:886-3-5780241 FAX:886-3-5794278.5770419 Email:support@weltrend.com.tw
WT6148/WT6160v1.02
Digital Monitor Controller
GENERAL DESCRIPTION
The WT6148/ WT6160 is a microcontroller for digital controlled monitor. It contains an 8-bit CPU, 48K /60K bytes ROM, 1056 bytes RAM, 14 PWMs, parallel I/Os, SYNC signal processor, timer, DDC1/2B interface, master/slave I2C interface, 6-bit A/D converter and watch-dog timer.
FEATURES
* 8-bit 6502 compatible CPU with 6MHz operating frequency * WT6148 : 48K bytes ROM, WT6160 : 60K bytes ROM, ,1024 bytes SRAM+32 bytes bit addressable SRAM * 12MHz crystal oscillator * 14 channels 8-bit PWM outputs * Sync signal processor with H+V separation, H/V frequency counter, H/V polarity detection/control and clamp pulse output * Six free-running sync signal outputs (Horizontal frequency up to 106KHz 85Hz@1600x1200) * Self-test pattern * DDC1/2B module for EDID1.3, EDID2.0 and Enhance EDID * Fast mode master/slave I2C interface (up to 400KHz) * Watch-dog timer * Maximum 28 programmable I/O pins * One 8-bit programmable timer * 6-bit A/D converter with 4 selectable inputs * One external interrupt request input * Low VDD reset
ORDERING INFORMATION
Package Type 42-pin PDIP 42-pin Shrink PDIP 40-pin PDIP 44-pin SOP 44-pin PLCC Part Number WT6148/ WT6160-N42 WT6148/ WT6160-K42 WT6148/ WT6160-N40 WT6148/ WT6160-S44 WT6148/ WT6160-L44
Weltrend Semiconductor, Inc.
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WT6148/WT6160v1.02
Digital Monitor Controller
PIN ASSIGNMENT AND PACKAGE TYPE
42-pin SPDIP
1 PWM2 PWM1 PWM0 RESET/3V3 VDD GND OSCO OSCI PB5/SDA2 PB4/SCL2 PB3/PAT PB2 PB1/HFI PB0/HFO IRQ PC7/SOGIN PC6 PC5 PC4 PC3/AD3 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 VIN HIN PWM3 PD5/PWM4 PD4/PWM5 PD3/PWM6 PD2/PWM7 PD1/HOUT PD0/VOUT PA7/PWM13/CLAMP PA6/PWM12 PA5/PWM11 PA4/PWM10 PA3/PWM9 PA2/PWM8 PA1/SCL1 PA0/SDA1 PC0/AD0 PC1/AD1 PC2/AD2 PWM2 PWM1 PWM0 RESET/3V3 VDD GND OSCO OSCI PB5/SDA2 PB4/SCL2 PB3/PAT PB2 PB1/HFI PB0/HFO IRQ PC7/SOGIN PC6 PC5 PC4 PC3/AD3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 VIN HIN PWM3 PD5/PWM4 PD4/PWM5 PD3/PWM6 PD2/PWM7 PD1/HOUT PD0/VOUT PA7/PWM13/CLAMP PA6/PWM12 PA5/PWM11 PA4/PWM10 PA3/PWM9 PA2/PWM8 PA1/SCL1 PA0/SDA1 PC0/AD0 PC1/AD1 PC2/AD2
40-pin PDIP
WT6148-K42 WT6160-K42
32 31 30 29 28 27 26 25 24 23 22
WT6148-N40 WT6160-N40
31 30 29 28 27 26 25 24 23 22 21
RESET/3V3
44-pin SOP
1 PWM2 PWM1 PWM0 RESET/3V3 VDD 2 3 4 5 6 7 GND OSCO OSCI PB5/SDA2 PB4/SCL2 PB3/PAT PB2 PB1/HFI PB0/HFO IRQ PC7/SOGIN PC6 PC5 PC4 PC3/AD3 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 PD3/PWM6 PD2/PWM7 PD1/HOUT PD0/VOUT PA7/PWM13/CLAMP PA6/PWM12 PA5/PWM11 PA4/PWM10 PA3/PWM9 PA2/PWM8 VIN HIN 6 PWM3 PD5/PWM4 PD4/PWM5 VDD GND OSCO OSCI PB5/SDA2 PB4/SCL2 PB3/PAT PB2 PB1/HFI PB0/HFO IRQ 7 8 9 10 11 12 13 14 15 16 17 18
44-pin PLCC
PWM0 PWM1 PWM2 PWM3 40 39 38 37 36 35 HIN 41 VIN 44 43 42 1
5
4
3
2
PD5/PWM4 PD4/PWM5 PD3/PWM6 PD2/PWM7 PD1/HOUT PD0/VOUT PA7/PWM13/CLAMP PA6/PWM12 PA5/PWM11 PA4/PWM10 PA3/PWM9
WT6148-S44 WT6160-S44
WT6148-L44 WT6160-L44
34 33 32 31 30 29
33 32 31 30 29 28 27 26 25 24 23
19
20
21
22
23
24
25
26
27 PA1/SCL1
PC6
PC5
PC4
PC3/AD3
PC2/AD2
PC1/AD1
PC0/AD0
PA0/SDA1
PA1/SCL1 PA0/SDA1 PC0/AD0 PC1/AD1 PC2/AD2
Weltrend Semiconductor, Inc.
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PC7/SOGIN
PA2/PWM8
28
WT6148/WT6160v1.02
Digital Monitor Controller PIN DESCRIPTION
Pin No. L44 S44 42 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Pin Name 40 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 6 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NC PWM2 PWM1 PWM0 /RESET NC VDD NC GND OSCO OSCI PB5/ SDA2 PB4/ SCL2 PB3/PAT PB2 PB1/HFI PB0/HFO /IRQ PC7/SOGIN PC6 PC5 PC4 PC3/AD3 PC2/AD2 PC1/AD1 PC0/AD0 PA0/SDA1 PA1/SCL1 PA2/PWM8 PA3/PWM9 PA4/PWM10 PA5/PWM11 PA6/PWM12 PA7/PWM13/ CLAMP PD0/VOUT PD1/HOUT PD2/PWM7 PD3/PWM6 NC PD4/PWM5 PD5/PWM4 PWM3 HIN VIN O O O I No Connection. PWM2 output (10V open-drain). PWM1 output (5V open-drain). PWM0 output (5V open-drain). Reset input No Connection. +5V power supply. No Connection. Ground. 12MHz oscillator output. 12MHz oscillator input. Port B5 or I2C interface data line. Port B4 or I2C interface clock line. Port B3 or test pattern output Port B2. Port B1 or half frequency divider input. Port B0 or half frequency divider output. Interrupt request input. A low level on this can generate interrupt. Port C7 or Sync on Green input. Port C6. Port C5. Port C4. Port C3 or ADC input 3. Port C2 or ADC input 2. Port C1 or ADC input 1. Port C0 or ADC input 0. Port A0 or DDC interface SDA pin. Port A1 or DDC interface SCL pin. Port A2 or PWM8 output. Port A3 or PWM9 output. Port A4 or PWM10 output. Port A5 or PWM11 output. Port A6 or PWM12 output. Port A7 or PWM13 output or clamp pulse output. I/O Description
I/O I I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Port D0 or Vsync output. Port D1 or Hsync output. Port D2 or PWM7 output. Port D3 or PWM6 output. No Connection. I/O Port D4 or PWM5 output. I/O Port D5 or PWM4 output. I/O PWM3 output (10V open-drain). I Hsync Input. I Vsync input.
Weltrend Semiconductor, Inc.
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WT6148/WT6160v1.02
Digital Monitor Controller
43 44 44 42 NC NC No Connection. No Connection.
FUNCTIONAL DESCRIPTION
CPU
8-bit 6502 compatible CPU operates at 6MHz. Address bus is 16-bit and data bus is 8-bit. The non-maskable interrupt (/NMI) of 6502 is modified to be maskable and is defined as INT0 with higher priority. The interrupt request (/IRQ) of 6502 is defined as INT1 with lower priority. Please refer the 6502 reference menu for more detail.
RAM
The 1024 bytes SRAM include : 128 bytes SRAM are from $0080H to $00FFH 256 bytes SRAM are from $0100H to $01FFH 256 bytes SRAM are from $0200H to $02FFH 256 bytes SRAM are from $0300H to $03FFH 128 bytes SRAM are from $0400H to $047FH The 32 bytes SRAM bit addressible are from $0500H to $05FFH
ROM
For WT6148, ROM address is located from $4000h to $FFFFh. For WT6160, ROM address is located from $1000h to $FFFFh. The following addresses are reserved for special purpose : $FFFAh (low byte) and $FFFBh (high byte) : INT0 interrupt vector. $FFFCh (low byte) and $FFFDh (high byte) : program reset interrupt vector. $FFFEh (low byte) and $FFFFh (high byte) : INT1 interrupt vector.
Weltrend Semiconductor, Inc.
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WT6148/WT6160v1.02
Digital Monitor Controller Memory Mapping
WT6148
$0000h : $003Fh $0040h : $007Fh $0080h : $00FFh $0100h : $01FFh $0200h : $02FFh $0300h : $03FFh Registers $0000h : $003Fh $0040h : $007Fh $0080h : $00FFh $0100h : $01FFh $0200h : $02FFh $0300h : $03FFh
WT6160
Registers
Reserved
Reserved
128 bytes RAM
128 bytes RAM
256 bytes RAM
256 bytes RAM
256 bytes RAM
256 bytes RAM
256 bytes RAM
256 bytes RAM
$0400h : 128 bytes RAM $047Fh $0480h : Reserved $04FFh $0500h Bit addressible : 32 bytes RAM $05FFh $0600h : Reserved $0FFEh $0FFFh Configuration Register $1000h : Reserved $3FFFh $4000h : : ROM : $FFFFh
$0400h : 128 bytes RAM $047Fh $0480h : Reserved $04FFh $0500h Bit addressible : 32 bytes RAM $05FFh $0600h : Reserved $0FFEh $0FFFh Configuration Register $1000h : : : ROM : : : $FFFFh
Weltrend Semiconductor, Inc.
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WT6148/WT6160v1.02
Digital Monitor Controller System Reset
There are four reset sources of this controller. Fig.1 shows the block diagram of reset logic.
RESET
Watchdog Timer Reset
LATCH
CPU
R
VDD
Low VDD Reset Peripheral Circuits
Address 6MHz
Illegal Address Reset 1.024ms Timer
Fig. 1 Reset Signals External Reset
A low level on the RESET pin will generate reset.
Illegal address Reset
When the address bus of CPU goes to illegal address, a reset pulse will be generated. The illegal address is defined as $0040h~$007Fh and $0600h~$0FFEh (and $1000h~$3FFFh for WT6148)
Low VDD Voltage Reset
When VDD is below 3.9V, an internal reset signal is generated. The reset signal will last 1.024 ms after the voltage is higher than 3.9V.
Watchdog Timer Reset
If a time-out happens when watchdog timer is enabled, a reset pulse is generated. Please refer watchdog timer section for more information.
Weltrend Semiconductor, Inc.
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WT6148/WT6160v1.02
Digital Monitor Controller I/O Port
I/O Port A
Pin PA0 and PA1 are shared with DDC interface SDA1 and SCL1 When ENDDC bit is "0", These two pins becomes I/O port. If PA0OE bit is set, Pin PA0 is an open-drain output. If PA0OE is cleared, Pin PA0 is an input pin with no internal pull-up resistor. The operation of PA1 is same as PA0. Fig. 2 Shows the structure of PA0.
INTERNAL_DATA_BUS DATA[0] D Q PA0OE PA0 WRITE_PA_CTRL RESET C R QN
DATA[0]
D
Q
PA0
WRITE_PA_DATA RESET
C R
QN
READ_PA_DATA DATA[0]
Fig.2 Structure of PA0 and PA1
Pin PA2 to PA6 are shared with PWM output. When corresponding EPWMx bit is "0", the pin is I/O port. If PAxOE bit is set, it is a push-pull type output. If PAxOE bit is cleared, it is an input pin with internal pull-up resistor. Pin PA7 is shared with PWM13 output and clamp pulse output. When both EPWM13 bit and ENCLP bit are "0", this pin becomes I/O port. If PA7OE bit is set, it is a push-pull type output. If PA7OE bit is cleared, it is an input pin with internal pull-up resistor.
INTERNAL_DATA_BUS DATA[2] D Q PA2OE
WRITE_PA_CTRL RESET
C R
QN PA2
DATA[2]
D
Q
PA2
WRITE_PA_DATA RESET
C R
QN
READ_PA_DATA DATA[2]
Fig.3 Structure of PA2
Weltrend Semiconductor, Inc.
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WT6148/WT6160v1.02
Digital Monitor Controller
Port A Control Register Name Addr R/W Initial
PA_CTRL 0000h W 00h
Bit 7
PA7OE
Bit 6
PA6OE
Bit 5
PA5OE
Bit4
PA4OE
Bit 3
PA3OE
Bit 2
PA2OE
Bit 1
PA1OE
Bit 0
PA0OE
Bit Name Description PAnOE Port An Output Enable. When it is set, PAn is output pin. When it is cleared, PAn is input pin with internal pull high (except PA0 and PA1 pins). Port A Data Register
Name Addr R/W Initial R W 00h 00h Bit 7 PA7 PA7 Bit 6 PA6 PA6 Bit 5 PA5 PA5 Bit4 PA4 PA4 Bit 3 PA3 PA3 Bit 2 PA2 PA2 Bit 1 PA1 PA1 Bit 0 PA0 PA0 PA_DATA 0001h
Bit Name Description PAn (W) This bit controls the output level when the corresponding PAnOE bit is set. When PAn=1, PAn pin outputs high level. (PA0 and PA1 are open-drain output) When PAn=0, PAn pin outputs low level. PAn (R) When PAnOE=1 (i.e. output port), this bit is same as PAn (W). When PAnOE=0, this bit indicates the input level. "1" means high and "0" means low.
I/O Port B
I/O Port B is shared with some special functions. When the special function is disabled, it is an general I/O port and is same as Port A2. If it is configured as an output, it can source/sink 6mA. If it is configured as an input, it has an internal pull-up resistor. Port B Control Register
Name Addr R/W Initial W 00h Bit 7 -Bit 6 -Bit 5 PB5OE Bit4 PB4OE Bit 3 PB3OE Bit 2 PB2OE Bit 1 PB1OE Bit 0 PB0OE PB_CTRL 0002h
Bit Name Description PBnOE Port Bn Output Enable. When it is set, PBn is output pin. When it is cleared, PBn is input pin with internal pull high Port B Data Register
Name Addr R/W Initial R W 00h 00h Bit 7 --Bit 6 --Bit 5 PB5 PB5 Bit4 PB4 PB4 Bit 3 PB3 PB3 Bit 2 PB2 PB2 Bit 1 PB1 PB1 Bit 0 PB0 PB0 PB_DATA 0003h
Bit Name Description PBn (W) This bit controls the output level when the corresponding PBnOE bit is set. When PBn=1, PBn pin outputs high level. When PBn=0, PBn pin outputs low level. PBn (R) When PBnOE=1 (i.e. output port), this bit is same as PBn (W). When PBnOE=0, this bit indicates the input level. "1" means high and "0" means low.
Weltrend Semiconductor, Inc.
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WT6148/WT6160v1.02
Digital Monitor Controller
Weltrend Semiconductor, Inc.
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Digital Monitor Controller
I/O Port C
The structure of I/O Port C is same as Port B except the output low level has 10mA current sink capability. Port C Control Register
Name Addr R/W Initial W 00h Bit 7 PC7OE Bit 6 PC6OE Bit 5 PC5OE Bit4 PC4OE Bit 3 PC3OE Bit 2 PC2OE Bit 1 PC1OE Bit 0 PC0OE PC_CTRL 0004h
Bit Name Description PCnOE Port Cn Output Enable. When it is set, PCn is output pin. When it is cleared, PCn is input pin with internal pull high Port C Data Register
Name Addr R/W Initial R W 00h 00h Bit 7 PC7 PC7 Bit 6 PC6 PC6 Bit 5 PC5 PC5 Bit4 PC4 PC4 Bit 3 PC3 PC3 Bit 2 PC2 PC2 Bit 1 PC1 PC1 Bit 0 PC0 PC0 PC_DATA 0005h
Bit Name Description PCn (W) This bit controls the output level when the corresponding PCnOE bit is set. When PCn=1, PCn pin outputs high level. When PCn=0, PCn pin outputs low level. PCn (R) When PCnOE=1 (i.e. output port), this bit is same as PCn (W). When PCnOE=0, this bit indicates the input level. "1" means high and "0" means low.
I/O Port D
I/O Port D is shared with some special functions. When the special function is disabled, it is an general I/O port and is same as Port A2. If it is configured as an output, it can source/sink 6mA. If it is configured as an input, it has an internal pull-up resistor. Port D Control Register
Name Addr R/W Initial W 00h Bit 7 -Bit 6 -Bit 5 PD5OE Bit4 PD4OE Bit 3 PD3OE Bit 2 PD2OE Bit 1 PD1OE Bit 0 PD0OE PD_CTRL 0006h
Bit Name Description PDnOE Port Dn Output Enable. When it is set, PDn is output pin. When it is cleared, PDn is input pin with internal pull high Port D Data Register
Name Addr R/W Initial R W x0h x0h Bit 7 --Bit 6 --Bit 5 PD5 PD5 Bit4 PD4 PD4 Bit 3 PD3 PD3 Bit 2 PD2 PD2 Bit 1 PD1 PD1 Bit 0 PD0 PD0 PD_DATA 0007h
Bit Name Description PDn (W) This bit controls the output level when the corresponding PDnOE bit is set. When PDn=1, PDn pin outputs high level. When PDn=0, PDn pin outputs low level.
Weltrend Semiconductor, Inc.
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WT6148/WT6160v1.02
Digital Monitor Controller
PDn (R) When PDnOE=1 (i.e. output port), this bit is same as PDn (W). When PDnOE=0, this bit indicates the input level. "1" means high and "0" means low.
Weltrend Semiconductor, Inc.
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WT6148/WT6160v1.02
Digital Monitor Controller SYNC Processor
The functional block diagram of Sync Processor is shown in Fig.4. It contains H and V polarity detection circuit, H and V frequency counter, composite sync signal separation circuit, free-running H and V sync signal generator, video signal generation circuit for burn-in test and clamp pulse generator.
SEPART
EXTRHS HIN H Polarity Detect Composite Signal Separator EXTRVS
MUX ENFREE
H Freq Counter
HINPOL
MUX FREEHS
H Polarity Control
HOUT
FREE1 FREE0
Free-running Sync Signal Generator
ENFREE FREEVS MUX SEPART
Clamp Pulse Generator
CLAMP
V Polarity Control VINPOL
VOUT
MUX VIN
V Polarity Detect
V Freq Counter PAT1 PAT0 Test Pattern Generator
PAT
Fig.4 Block diagram of sync signal processor
Horizontal Polarity Detect
The horizontal polarity is detected by sampling HIN signal at 4.5~5.5us after rising and falling edge of HIN. If the result of sampling is low and lasts 768~1024us with no change, the polarity is positive (HINPOL=1). If the result of sampling is high and lasts 768~1024us with no change, the polarity is negative (HINPOL=0). The maximum detectable HIN frequency is 154kHz if the HIN pulse width is under 1us.
Vertical Polarity Detect
Vertical polarity is detected by sampling VIN level at 1.024ms after rising edge of VIN. If the level is low, the polarity is positive (VINPOL=1). If the level is high, the polarity is negative (VINPOL=0). But if SEPART bit is set, the VINPOL bit is "1" because the Vsync from composite signal separator is always positive polarity.
Output Polarity Control
The polarities of HOUT and VOUT are controlled by HOPOL and VOPOL bites. When the bit is set, the output polarity is positive. When the bit is cleared, the output polarity is negative.
Weltrend Semiconductor, Inc.
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WT6148/WT6160v1.02
Digital Monitor Controller
Horizontal frequency counter
A 12-bit counter is used to measure horizontal frequency. User can choose 16ms or 32ms time interval to count pulse number of Hsync every 16.384ms or 32.768ms. For example, if QUICK bit is set, when a 16.384ms time frame begins, it resets the counter and starts counting Hsync pulses till 16ms reached, then loads the counter value to HFREQ_H and HFREQ_L registers. If the H frequency is over 125KHz, the H counter will set overflow flag (HOVF ) to "1". If the H frequency is over 187.5KHz, the H counter will stop counting. Therefore the measured H frequency is equal to 125kHZ plus HFREQ_H and HFREQ_L The sync processor interrupt is generated every 16.384ms or 32.768ms for checking H frequency. This interrupt will be cleared after reading the HFREQ_H register.
Hsync Interrupt Hfreq Counter Enable 16/32 ms 16.384/32.768 ms Hfreq Counter Clock Fig.5 Horizontal Frequency Counter timing
Horizontal Frequency Register
Name Addr R/W Initial R R xxh xxh Bit 7 HLVL HOVF Bit 6 HINPOL HFH6 Bit 5 -HFH5 Bit4 HFL4 HFH4 Bit 3 HFL3 HFH3 Bit 2 HFL2 HFH2 Bit 1 HFL1 HFH1 Bit 0 HFL0 HFH0 HFREQ_L 0008h HFREQ_H 0009h
Description "1" : Indicates Hsync pin is high level. "0" : Indicates Hsync pin is low level. HINPOL "1" : Indicates Hsync input is positive polarity. "0" : Indicates Hsync input is negative polarity. HOVF Indicates H counter is overflowed (over 125KHz) when this bit is set. HFH6 ...HFH0 Indicates the Hsync frequency in kHz. HFL4 ... HFL0 When QUICK="0", HFL4 ~ HFL0 indicates the Hsync frequency in 31.25Hz unit. When QUICK="1", HFL4 ~ HFL1 indicates the Hsync frequency in 62.5Hz. Example of Hsync Frequency Calculation QUICK="0" HFH6..0 HFL4..0 Max. Freq Min. Freq $40h $00000b 64.0313KHz 63.9687KHz $40h $00001b 64.0625KHz 64.0000KHz $40h $00010b 64.0938KHz 64.0312KHz $40h $00011b 64.1250KHz 64.0625KHz $51h $10000b 81.5313KHz 81.4687KHz $51h $10001b 81.5625KHz 81.5000KHz $51h $10010b 81.5938KHz 81.5312KHz $51h $10011b 81.6250KHz 81.5625KHz
Bit Name HLVL
HFH6..0 $40h $40h $51h $51h
QUICK="1" HFL4..0 Max. Freq Min. Freq $0000xb 64.0625KHz 63.9375KHz $0001xb $1000xb $1001xb 64.1250KHz 64.0000KHz 81.5625KHz 81.4375KHz 81.6250KHz 81.5000KHz
Weltrend Semiconductor, Inc.
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WT6148/WT6160v1.02
Digital Monitor Controller
Vertical frequency counter
A 13-bit counter is used to measure the time interval between two vertical sync pulses. It will be updated every vertical frame. The clock of this counter is 125kHz. So the frequency of Vsync is [125000 / (counter value + 1)] Hz. When V frequency is lower than 15.25Hz, this counter stops counting and set VOVF bit to "1". Vertical Frequency Register
Name Addr R/W Initial R R xxh xxh Bit 7 VF7 VLVL Bit 6 VF6 VINPOL Bit 5 VF5 VOVF Bit4 VF4 VF12 Bit 3 VF3 VF11 Bit 2 VF2 VF10 Bit 1 VF1 VF9 Bit 0 VF0 VF8 VFREQ_L 000Ah VFREQ_H 000Bh
Bit Name Description VLVL "1" : Indicates Vsync pin is high level. "0" : Indicates Vsync pin is low level. VNPOL "1" : Indicates Vsync input is positive polarity. "0" : Indicates Vsync input is negative polarity. VOVF Indicates V counter is overflowed when this is set. Vsync frequency is lower than 15.25Hz VF12 ~ VF0 Indicates the Vertical Total Time. Vertical frequency is [125000 / (counter value +1) ] Hz Example of Vsync Frequency Calculation VF12..0 Max. Freq Min. Freq $05BDh 85.15Hz 85.034Hz $05BEh 85.092Hz 84.976Hz $05BFh 85.034Hz 84.918Hz $0681h 75.12Hz 75.03Hz $0682h 75.075Hz 74.985Hz $0683h 75.03Hz 74.94Hz $06C7h 72.088Hz 72.005Hz $06C8h 72.046Hz 71.963Hz $06C9h 72.005Hz 71.921Hz
VF12..0 $0783h $0784h $0785h $0823h $0824h $0825h $1FFEh $1FFEh $1FFFh
Max. Freq 65.036Hz 65.003Hz 64.969Hz 60.038Hz 60.01Hz 59.981Hz 15.266Hz 15.264Hz 15.262Hz
Min. Freq 64.969Hz 64.935Hz 64.901Hz 59.981Hz 59.952Hz 59.923Hz 15.262Hz 15.260Hz 15.258Hz
Hsync period counter
This is an 8-bit counter that uses 6MHz clock to measure time interval between two H pulses. If the H frequency is lower than 23437.5Hz, this counter will overflow and register H_PERD value is zero. Horizontal Period Register
Name Addr R/W Initial xxh Bit 7 HPRD7 Bit 6 HPRD6 Bit 5 HPRD5 Bit4 HPRD4 Bit 3 HPRD3 Bit 2 HPRD2 Bit 1 HPRD1 Bit 0 HPRD0 H_PERD 000Ch R
Bit Name
HPRD7 .. 0
Description H freq = 6MHz / (counter value+1)
Example of Hsync Frequency Calculation HPRD7..0 Max. Freq Min. Freq HPRD7..0 $49h 83.333KHz 81.081KHz $7Ch $4Ah 82.192KHz 80KHz $7Dh $4Bh 81.081KHz 78.947KHz $7Eh $5Dh 65.217KHz 63.83KHz $BFh $5Eh 64.516KHz 63.158KHz $C0h $5Fh 63.83KHz 62.5KHz $C1h
Max. Freq 48.78KHz 48.387KHz 48KHz 31.579KHz 31.414KHz 31.25KHz
Min. Freq 48KHz 47.619KHz 47.244KHz 31.25KHz 31.088KHz 30.928KHz
Weltrend Semiconductor, Inc.
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WT6148/WT6160v1.02
Digital Monitor Controller
Composite Sync Signal Separator
Composite sync signal separator extract Vsync signal from HIN or SOGIN input pin by filtering pulses which is less than 6us. The output Vsync signal will be widened about 4.5~5.5us. The output Hsync will be replaced by 2us pulse during Vsync pulse. The composite sync signal separator can handle H+V and H exclusive OR V signals. Fig.5 shows the timing relationship of the extracted H and V sync signals. If Hsync output do not want to insert pseudo H pulses (EXTRHS signal) during Vsync pulse, set BYPASS bit can let HOUT pin output waveform same as Hsync input (Note: polarity can be controlled by HOPOL bit).
Hsync Vsync H+V H XOR V Bypass H pulse EXTRHS 2us EXTRVS 4.5~5.5us Hsync 2us Insert H pulse Bypass H pulse
Vsync H EORV Bypass H pulse EXTRHS 2us EXTRVS 4.5~5.5us 2us Insert H pulse Bypass H pulse
Fig. 6 Timing relationship of composite sync signal separator
Weltrend Semiconductor, Inc.
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WT6148/WT6160v1.02
Digital Monitor Controller
Free-running sync signal and self-test pattern
The self-generated free run sync signals are output from HOUT and VOUT pins when ENFREE bit is set. Four kinds of standard VESA timings are selected by FREE1 and FREE0 bits. Self-test pattern signal is output from PAT pin when ENPAT bit is set. PAT1 and PAT0 bits select different self-test pattern.
PAT1 = 0, PAT0 = 0
PAT1 = 0, PAT0 = 1
PAT1 = 1, PAT0 = 0
PAT1 = 1, PAT0 = 1
Fig.7 Test Pattern
FREE2,1,0 bit value FH FV THT TVT THS THB THF TVS TVB TVF TVIDEO X00 X01 48KHz 72.072Hz 20.833us 13.875ms 2.417us 1.417us 1.125us 6 x THT 23 x THT 38 x THT 41.67ns THS 010 63.83KHz 59.878Hz 15.667us 16.7ms 1us 2.417us 0.542us 3 x THT 38 x THT 3 x THT 41.67ns 011 81.25KHz 64.865Hz 12.333us 15.417ms 1.083us 1.833us 0.375us 3 x THT 46 x THT 2 x THT 41.67ns 110 111
Hor frequency 31.496KHz Ver frequency 59.993Hz Hor total time 31.75us Ver total time 16.669ms H sync time 3.833us H Back porch + 2 us H Left border H Front porch + 0.708us H Right border V sync time 2 x THT V Back porch + 33 X THT V Top border V Front porch + 11 x THT V Bottom border Video pulse width 41.67ns THT
90.909KHz 106.195KHz 84.8Hz 84.96Hz 11us 9.417us 11.792ms 11.771ms 1us 0.833us 1.583us 1.417us 0.375us 3 x THT 44 x THT 2 x THT 41.67ns 0.292us 3 x THT 46 x THT 2 x THT 41.67ns
HOUT VOUT
TVS TVT THT THS
HOUT PAT THB THB THF TVEDIO
Fig.8 Free-running sync signal and test pattern timing
Weltrend Semiconductor, Inc.
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WT6148/WT6160v1.02
Digital Monitor Controller
Clamp pulse
Clamp pulse is generated on either rising or falling edge of HOUT pin by setting the CLPEG bit. The pulse width of clamp is specified by CLPPW bit. Output polarity is specified by CLPPO bit. HOUT CLAMP
CLPPO=1 0.542~0.625us/2.042~2.125us
CLAMP
CLPPO=0 0.542~0.625us/2.042~2.125us
Fig. 9a Clamp pulse waveform (CLPEG=1)
HOUT CLAMP
CLPPO=1 0.542~0.625us/2.042~2.125us
CLAMP
CLPPO=0 0.542~0.625us/2.042~2.125us
Fig. 9b Clamp pulse waveform (CLPEG=0)
Sync Processor Control Registers
Name HV_CR1 HV_CR2 HV_CR3 Addr R/W Initial 0008h 0009h 000Ah W W W Bit 7 Bit 6 Bit 5 HOPOL CLPPO -Bit4 VOPOL CLPPW -Bit 3 Bit 2 Bit 1 Bit 0 00h ENHOUT ENVOUT 00h ENCLP CLPEG x0h --QUICK SEPART ENFREE ENPAT FREE1 FREE0 PAT1 PAT0 -SOG FREE2 BYPASS
Bit Name ENHOUT ENVOUT HOPOL VOPOL QUICK SEPART ENFREE ENPAT ENCLP
Description "1" : Enable HOUT. "0" : Disable HOUT. Pin is configured as I/O port PD1. "1" : Enable VOUT. "0" : Disable VOUT. Pin is configured as I/O port PD0. "1" : HOUT is positive polarity. "0" : HOUT is negative polarity. "1" : VOUT is positive polarity. "0" : VOUT is negative polarity. "1" : Select 16ms time interval to count H pulses every 16.384ms. "0" : Select 32ms time interval to count H pulses every 32.768ms. "1" : Enable sync separator circuit and use the extracted Vsync signal as VOUT. "0" : VOUT pin outputs Vsync from VIN pin Enable free-running sync signal output on HOUT and VOUT pins when this bit is set. "1" : Enable self-test pattern output on PAT pin when this bit is set. "0" : Disable test pattern output. Pin is configured as I/O port PB3. "1" : Enable clamp pulse output on CLAMP pin. "0" : Disable clamp pulse output. Pin is configured as I/O port PA7.
Weltrend Semiconductor, Inc.
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WT6148/WT6160v1.02
Digital Monitor Controller
CLPEG CLPPO "1" : Clamp pulse follows HOUT signal's rising edge. "0" : Clamp pulse follows HOUT signal's falling edge. Select polarity of clamp pulse. "1" : Positive polarity "0" : Negative polarity Select pulse width of clamp pulse. "1" : 2us "0" : 0.5us Select free-running sync signal frequency. "111" : 1600x1200@85Hz H = 106.25kHz, V = 85Hz "110" : 1280x1024@85Hz H = 91kHz, V = 85Hz "011" : 1600x1200@65Hz H = 81kHz, V = 65Hz "010" : 1280x1024@60Hz H = 64kHz, V = 60Hz "x01" : 800x600@72Hz H = 48kHz, V = 72Hz "x00" : 640x480@60Hz H = 31.4kHz, V = 60Hz Select test pattern. "00" : White picture "01" : 2x2 cross hatch "10" : Black picture "11" : Inverse 2x2 cross hatch Select composite sync signal input source. "1" : Composite sync signal comes from SOGIN pin. "0" : Composite sync signal comes from HIN pin. Select bypass the composite signal separator or not. "1" : HOUT pin outputs sync signal bypass the composite signal separator. "0" : HOUT pin outputs sync signal from the composite signal separator.
CLPPW
FREE2,1,0
PAT1,0
SOG
BYPASS
Weltrend Semiconductor, Inc.
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WT6148/WT6160v1.02
Digital Monitor Controller
Half Frequency Function
When ENHLFIO bit is set, Pin PB1 becomes half frequency input (HLFI) and Pin PB0 becomes half frequency output (HLFO). The HALF bit controls the divided-by-two function is enabled or not.
HLFI HLFO (HALF=0) (HLFPO=0) HLFO (HALF=0) (HLFPO=1) HLFO (HALF=1)
HLF_POL
HALF
HLFO
D
Q
HLFI
C
QN
Fig. 10 Half Hsync frequency Half Frequency Output Control Register
Name Addr R/W Initial x0h Bit 7 -Bit 6 -Bit 5 -Bit4 -Bit 3 -Bit 2 ENHFIO Bit 1 HALF Bit 0 HF_POL HLF_CON 000Dh W
Bit Name ENHFIO
HALF HF_POL
Bit Description Enable half frequency input and output pins. "1" : PB1 and PB0 pins are half frequency input and output pins. "0" : PB1 and PB0 pins are I/O port. "1" : HLFO pin outputs half frequency from HLFI pin. "0" : HLFO pin outputs same frequency from HLFI pin. "1" : HLFO polarity is same as HLFI. "0" : HLFO polarity is not same as HLFI.
Weltrend Semiconductor, Inc.
Page 20
WT6148/WT6160v1.02
Digital Monitor Controller DDC Interface
The DDC interface is a slave mode I2C interface with DDC1 function. It is compatible with VESA DDC1/2B standard. This interface not only can be used for DDC communication, but also can be applied for factory alignment purpose. When ENDDC bit is set, the outputs of SDA1 and SCL1 pins are open-drain type. The DDC function depends on the DDC2 bit value. If DDC2 bit is "0", it is in DDC1 state. If DDC2 bit is "1", it is in DDC2 state In DDC1 state, the data is shifted out to SDA1 pin on the rising edge of VSYNC clock. Data format is an 8-bit byte followed by a null bit (always "1"). Most significant bit (MSB) is transmitted first. Every time when the ninth bit has been transmitted, the shift register will load a data byte from data buffer (DDC_TX register). After loading data to the shift register, the data buffer becomes empty and generates an interrupt. Program can check DDCRDY bit to load new data byte. If a high to low transition occurs on SCL1 in DDC1 state, the SCLH2L bit will be set and generate an interrupt. Program can set DDC2 bit to enter DDC2 state. If no valid DDC2 command is received within a certain time (for example, 128 Vsync clocks or 2sec), program should clear DDC2 bit and back to DDC1 state to avoid noise interference. The data format of DDC2 is S Address R/W A D7,D6,...., D0 A D7,D6,...., D0 A P
S : Start condition. A falling edge on SDA1 pin when SCL1 pin is high level. P : Stop condition. A rising edge on SDA1 pin when SCL1 pin is high level. A : Acknowledge bit. "0" means acknowledge and "1" means non-acknowledge. Address : 7-bit device address. R/W : Read/Write control bit, "1" is read and "0" is write. D7,D6,...., D0 : data byte. In DDC2 state, after START and valid address is received, it send out ACK("0") if the TXNAK1 bit is "0". Otherwise the SDA1 pin outputs NACK("1"). An interrupt will be generated after sending ACK bit and SCL1 pin is pulled low to stop the clock for handshaking. In the interrupt routine, write DDC_AR0 register will stop pulling low the SCL1 pin and clear the interrupt. The received address byte can be read in DDC_RX register and also can use MATCH bit to identify what address is received. The Write or Read operation can be checked by reading the DDCRW bit. Write operation After received the first byte (address byte), interrupt routine finds it is the first byte (FIRST=1) and write operation (DDCRW=0), program should clear TX bit to "0" (for receiving data) and write DDC_AR0 register (to release the SCL1 pin). Then the host sends out a data byte and SDA1 pin outputs ACK if TXNACK bit is "0". An interrupt is generated after the ACK bit to inform CPU to read DDC_RX register. When host finished transferring data, it will send STOP condition. When STOP condition is detected, the STOP bit will be set and generates an interrupt. The interrupt routine can use the STOP bit to know the data transfer is finished and start executing the received command. Read operation After received the first byte (address byte), interrupt routine finds it is the first byte (FIRST=1) and read operation (DDCRW=1), program should set TX bit to "1", write data to DDC_TX register and write DDC_AR0 register (to release the SCL1 pin). The host will output ACK after received a data byte. When host wants to finish reading, it outputs NACK to stop communication. Program can read the RXACK1 bit to check the acknowledge bit that host sends.
Weltrend Semiconductor, Inc.
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WT6148/WT6160v1.02
Digital Monitor Controller
DDC1 Timing
(1) DDC1 transmit :
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
VSYNC SDA
load data to shift register
data "FFH"
N
data "FFH"
N
EDID data 1
N
EDID data 2
INT0
write REG#14H to clear DDCRDY
set ENDDC
DDCRDY=1 SCLH2L=0 DDC2=0 FIRST=0 STOP=0 DDC2RW=0 MATCH=0 RXNAK1=0
DDCRDY=1 SCLH2L=0 DDC2=0 FIRST=0 STOP=0 DDC2RW=0 MATCH=0 RXNAK1=0
DDCRDY=1 SCLH2L=0 DDC2=0 FIRST=0 STOP=0 DDC2RW=0 MATCH=0 RXNAK1=0
(2) DDC1 to DDC2 transition (I) :
VSYNC SDA SCL INT0
set CLRH2L,clear CLRH2L to clear DDCRDY
START
EDID data
N
EDID data
Slave Address
0A
Pull low SCL
DDCRDY=1 SCLH2L=0 DDC2=0 FIRST=0 STOP=0 DDC2RW=0 MATCH=0 RXNAK1=0
DDCRDY=1 SCLH2L=1 DDC2=1 FIRST=1 STOP=0 DDC2RW=0 MATCH=0 RXNAK1=0
DDCRDY=1 SCLH2L=0 DDC2=1 FIRST=1 STOP=0 DDC2RW=0 MATCH=0,1 RXNAK1=0
(3) DDC1 to DDC2 transition (II) :
START
VSYNC SDA SCL INT0
set CLRH2L,clear CLRH2L to clear DDCRDY
DDCRDY=1 SCLH2L=0 DDC2=0 FIRST=0 STOP=0 DDC2RW=0 MATCH=0 RXNAK1=0 DDCRDY=1 SCLH2L=1 DDC2=1 FIRST=1 STOP=0 DDC2RW=0 MATCH=0 RXNAK1=0 DDCRDY=1 SCLH2L=0 DDC2=1 FIRST=1 STOP=0 DDC2RW=0 MATCH=0,1 RXNCK1=0
EDID data
N
EDID data
Slave Address
WA
Pull low SCL
Weltrend Semiconductor, Inc.
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WT6148/WT6160v1.02
Digital Monitor Controller
DDC2 Timing
(1) Write mode :
START
SCL SDA
SDA output
Pull low SCL
Pull low SCL
Pull low SCL
STO P
Slave Address
0A
RX DATA 1
A
RX DATA 2
A
A
A
A
INT0
write REG#16H to release SCL
DDCRDY=1 SCLH2L=0 DDC2=1 FIRST=1 STOP=0 DDC2RW=0 MATCH=0,1 RXNAK1=0
DDCRDY=1 SCLH2L=0 DDC2=1 FIRST=0 STOP=0 DDC2RW=0 MATCH=0,1 RXNAK1=0
DDCRDY=1 SCLH2L=0 DDC2=1 FIRST=0 STOP=0 DDC2RW=0 MATCH=0,1 RXNAK1=0
DDCRDY=1 SCLH2L=0 DDC2=1 FIRST=0 STOP=1 DDC2RW=0 MATCH=0,1 RXNAK1=0
(2) Read mode (I) :
START
SCL SDA
SDA output
Pull low SCL
Pull low SCL
Pull low SCL
STO P
Slave Address
1A
A
TX DATA 1 TX DATA 1
SET TX
A
TX DATA 2 TX DATA 2
N
INT0
write REG#16H to release SCL
DDCRDY=1 SCLH2L=0 DDC2=1 FIRST=1 STOP=0 DDC2RW=1 MATCH=0,1 RXNAK1=0
DDCRDY=1 SCLH2L=0 DDC2=1 FIRST=0 STOP=0 DDC2RW=1 MATCH=0,1 RXNAK1=0
DDCRDY=1 SCLH2L=0 DDC2=1 FIRST=0 STOP=0 DDC2RW=1 MATCH=0,1 RXNAK1=1
DDCRDY=1 SCLH2L=0 DDC2=1 FIRST=0 STOP=1 DDC2RW=1 MATCH=0,1 RXNAK1=1
(3) Read mode (II) :
START
SCL SDA
SDA output
Pull low SCL
Pull low SCL
Pull low SCL
STO P
Slave Address
1A
RX DATA
A
A
A
TX DATA TX DATA
SET TX
N
INT0
write REG#16H to release SCL
DDCRDY=1 SCLH2L=0 DDC2=1 FIRST=1 STOP=0 DDC2RW=1 MATCH=0,1 RXNAK1=0 DDCRDY=1 SCLH2L=0 DDC2=1 FIRST=0 STOP=0 DDC2RW=1 MATCH=0,1 RXNAK1=0
DDCRDY=1 SCLH2L=0 DDC2=1 FIRST=0 STOP=0 DDC2RW=1 MATCH=0,1 RXNAK1=1
DDCRDY=1 SCLH2L=0 DDC2=1 FIRST=0 STOP=1 DDC2RW=1 MATCH=0,1 RXNAK1=1
Weltrend Semiconductor, Inc.
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WT6148/WT6160v1.02
Digital Monitor Controller
DDC Address 0 Enable Register
Name Addr R/W Initial W Bit 7 Bit 6 Bit 5 Bit4 Bit 3 Bit 2 Bit 1 Bit 0
DDC_A0E 0013h
FFh ENADR07 ENADR06 ENADR05 ENADR04 ENADR03 ENADR02 ENADR01 ENADR00
Bit Name ENADR07 ENADR06 ENADR05 ENADR04 ENADR03 ENADR02 ENADR01 ENADR00
Description Enable (DAR07~ DAR04 +"111xB") address to be compared when it is set. Enable (DAR07~ DAR04 +"110xB") address to be compared when it is set. Enable (DAR07~ DAR04 +"101xB") address to be compared when it is set. Enable (DAR07~ DAR04 +"100xB") address to be compared when it is set. Enable (DAR07~ DAR04 +"011xB") address to be compared when it is set. Enable (DAR07~ DAR04 +"010xB") address to be compared when it is set. Enable (DAR07~ DAR04 +"001xB") address to be compared when it is set. Enable (DAR07~ DAR04 +"000xB") address to be compared when it is set.
DDC Receive Buffer Register
Name Addr R/W Initial R FFh Bit 7 DRX7 Bit 6 DRX6 Bit 5 DRX5 Bit4 DRX4 Bit 3 DRX3 Bit 2 DRX2 Bit 1 DRX1 Bit 0 DRX0 DDC_RX 0014h
Bit Name Description DRX7 ... DRX0 DDC received data is stored in this register. DDC Transmit Buffer Register
Name Addr R/W Initial FFh Bit 7 DTX7 Bit 6 DTX6 Bit 5 DTX5 Bit4 DTX4 Bit 3 DTX3 Bit 2 DTX2 Bit 1 DTX1 Bit 0 DTX0 DDC_TX 0014h W
Bit Name Description DTX7 ... DTX0 This register stores the data to be transmitted DDC Status Register
Name Addr R/W Initial R Bit 7 Bit 6 Bit 5 DDC2 Bit4 FIRST Bit 3 STOP Bit 2 DDC2RW Bit 1 MATCH Bit 0 RXNAK1 DDC_STA 0015h 01h DDCRDY SCLH2L
Bit Name DDCRDY SCLH2L DDC2(R) FIRST STOP DDC2RW
MATCH RXNAK1
Description When it is set, data buffer is ready to read/write or a SCL1 high to low transition in DDC1 state. Indicates a high to low transition on SCL1 pin in DDC1 state when it is set. "1" : Indicates it is in DDC2 state. "0" : Indicates it is in DDC1 state. Indicates the first byte (address) is received when this bit is set. Indicates STOP condition is received when this bit is set. Indicates the received R/W bit after 7-bit address. "1" : Read "0" : Write "1" : Address is equal to Address Register 1 or Address Register 2. "0" : The most significant 4 bits are equal to Address Register 0. Indicates the received acknowledge bit. "1" : NACK "0" : ACK
Weltrend Semiconductor, Inc.
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WT6148/WT6160v1.02
Digital Monitor Controller
DDC Control Register
Name Addr R/W Initial 00h Bit 7 Bit 6 Bit 5 DDC2 Bit4 -Bit 3 -Bit 2 TX Bit 1 -Bit 0 TXNAK1 DDC_CON 0015h W ENDDC CLRH2L
Bit Name ENDDC CLRH2L DDC2(W) TX TXNAK1
Description "1" : Enable DDC interface. PA0 and PA1 are configured as DDC interface. "0" : Disable DDC interface. PA0 and PA1 are configured as I/O port. Set this bit will reset SCLH2L bit. "1" : Set DDC2. "0" : Set DDC1. "1" : Set transmit direction. "0" : Set receive direction. Determines the ACK bit to be transmitted. "1" : Transmit NACK. "0" : Transmit ACK.
DDC Address Register 0
Name Addr R/W Initial X0h Bit 7 DAR07 Bit 6 DAR06 Bit 5 DAR05 Bit4 DAR04 Bit 3 -Bit 2 -Bit 1 -Bit 0 ENAR0 DDC_AR0 0016h W
Bit Name DAR07~ DAR04 ENAR0
Description 4-bit DDC address to be compared. DAR07 is compared with the MSB of the received address. Enable DAR07- DAR04 to be compared when this bit is set.
DDC Address Register 1
Name Addr R/W Initial X0h Bit 7 DAR17 Bit 6 DAR16 Bit 5 DAR15 Bit4 DAR14 Bit 3 DAR13 Bit 2 DAR12 Bit 1 DAR11 Bit 0 ENAR1 DDC_AR1 0017h W
Bit Name DAR17~ DAR11 ENAR1
Description 7-bit DDC address to be compared. DAR17 is compared with the MSB of the received address. Enable DAR17- DAR11 to be compared when this bit is set.
DDC Address Register 2
Name Addr R/W Initial X0h Bit 7 DAR27 Bit 6 DAR26 Bit 5 DAR25 Bit4 DAR24 Bit 3 DAR23 Bit 2 DAR22 Bit 1 DAR21 Bit 0 ENAR2 DDC_AR2 0019h W
Bit Name DAR27~ DAR21 ENAR2
Description 7-bit DDC address to be compared. DAR27 is compared with the MSB of the received address. Enable DAR27- DAR21 to be compared when this bit is set.
Weltrend Semiconductor, Inc.
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WT6148/WT6160v1.02
Digital Monitor Controller
DDC Flow Chart
START
set ENDDC (W15.7) "xxxxxxxxB' =>DDC_AR0E(W13) slave I address =>DDC_AR0(W16) slave II address =>DDC_AR1(W17) slave III address =>DDC_AR2(W19)
No
DDCRDY (R15.7) =1?
Yes No
DDC2(R15.5) =1?
Yes
DDC data => DDC_TX(W14)
DDC 1
No
No
SCLH2L (R15.6) =1?
Yes
SCLH2L (R15.6) =1?
Yes
set CLRH2L (W15.6) & DDC2(W15.5) #11100000B => W15 clear CLRH2L (W15.6) #10100000B => W15
DDC1 => DDC2
DDCRDY (R15.7) =1?
No
Yes
No
128 Vsync or 2 s ?
Yes
clear DDC2 (W15.5) #10000000B => W15
MATCH(R15.1) =0?
Yes
No
DDC_RX(R14)=Slave II address?
Yes
No
DDC 2
slave III address subprogram
slave II address subprogram
FIRST(R15.4) =1?
Yes
No
read DDC_RX(R14) slave I address=A0 or A2or A4 or A6
STOP (R15.3) =1?
Yes
No
slave I address=>DDC_AR0(W16)
No
DDC2RW (R15.2) =1? DDC2RW (R15.2) =1?
Yes No Yes
No
read DDC_RX(R14)
RXNACK1 (R15.0) =0? slave I address=>DDC_AR0(W16)
Yes
set TX(W15.2) DDC data => DDC_TX(W14)
DDC data => DDC_TX(W14) slave I address=>DDC_AR0(W16) slave I address=>DDC_AR0(W16)
Weltrend Semiconductor, Inc.
Page 26
WT6148/WT6160v1.02
Digital Monitor Controller Master/Slave I2C interface
The master/slave I2C interface is provided for communicating with other I2C devices in the monitor such as EEPROM, OSD, deflection IC and so on.
Master Mode
To choose master mode, clear the SLAVE bit. The clock frequency can be programmed to 50KHz, 100kHz, 200kHz or 400KHz by setting MCLK1 and MCLK2 bits. Send out START and the first byte (START, 7-bit address and R/W bit) First, clear I2CRW bit to select transmitter mode and write first byte (7-bit address and R/W bit) to MI2C_TX register. Then set MSTR bit, master will generate a START condition and send out the first byte with the clock speed specified in MCLK1 and MCLK2 bits. After the whole data byte is transmitted and the 9th bit is received, the MI2CRDY bit is set and generates an interrupt if it is enabled. The 9th bit will be stored in RXNAK2 bit for checking the slave acknowledge or not. The SCL2 pin will keep low to wait next byte operation. Send out the following bytes If it is a write command, write a data byte to MI2C_TX register, then write any value to I2C_AR register to clear MI2CRDY bit. It will send out the data byte and store the acknowledge bit from slave in RXACK2 bit. Again, the MI2CRDY bit is set after the acknowledge bit is received. If it is a read command, set I2CRW bit to be receiver mode and write TXACK2 bit to determine what will be sent on acknowledge bit, then write MI2C_AR register to clear I2CRDY bit and it will send out the clock for receiving next byte. After the acknowledge bit is transmitted, the I2CRDY bit will be set. If master wants to stop the read operation, send NACK on acknowledge bit to inform slave device. Send out STOP Set MSTOP bit will generate STOP condition.
Slave Mode
The slave mode operation is same as DDC interface in DDC2 state. First, set the SLAVE bit and set the I2CRW bit to be receiver mode. When CPU is ready to receive, clear TXNAK2 bit. It will response ACK when a START condition followed by an address (which is equal to I2C_ADR register) are received. An interrupt can be generated if it is enabled and the R/W bit is stored in SRW bit for checking read/write operation. After the ACK bit, SCL2 pin outputs low level to stop the clock for handshaking. Add the function that one master access multi-slave when WT6148/ WT6160 in slave mode If a write command is received (SRW bit=0), read the I2C_RX register, clear I2CRW bit to receive next byte, then write I2C_ADR to clear I2CRDY bit and stop pulling low the SCL2 pin for receiving next byte from master. The output acknowledge bit is controlled by TX NAK2 bit. If a read command is received (SRW bit=1), write data to I2C_TX register, clear I2CRW bit and write I2C_ADR register to clear I2CRDY bit and stop pulling low the SCL2 pin for master sending out clock The received acknowledge bit is stored in RXNAK2 bit.
Weltrend Semiconductor, Inc.
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WT6148/WT6160v1.02
Digital Monitor Controller
Master I2C Data Sequence
(1) Write mode :
START MSCL MSDA
MSDA output
Pull low MSCL
Pull low MSCL
Pull low MSCLSTOP
A
Slave Address Slave Address
SET MSTR
0A 0
TX DATA 1 TX DATA 1
A
TX DATA 2 TX DATA 2
SET
I2CRDY
MSTOP
write REG#12H to release MSCL
BB=1 RXNAK2=0 I2CRDY=1
BB=1 RXNAK2=0 I2CRDY=1
BB=1 RXNAK2=0 I2CRDY=1
BB=0
(2) Read mode (I) :
START MSCL MSDA
MSDA output Pull low MSCL Pull low MSCL Pull low MSCL
STOP
Slave Address Slave Address
SET MSTR
1A 1
RX DATA 1
SET I2CRW
A A
RX DATA 2
SET TXNAK2
N N
SET
I2CRDY
MSTOP
write REG#12H to release MSCL
BB=1 RXNAK2=0 I2CRDY=1
BB=1 RXNAK2=0 I2CRDY=1
BB=1 RXNAK2=1 I2CRDY=1
BB=0
(3) Read mode (II) :
START MSCL MSDA
MSDA output Pull low MSCL Pull low MSCL Pull low MSCL
STOP
Slave Address Slave Address
SET MSTR
1A 1
TX DATA TX DATA
A
RX DATA
SET I2CRW SET TXNAK2
N
N
SET
I2CRDY
MSTOP
write REG#12H to release MSCL
BB=1 RXNAK2=0 I2CRDY=1
BB=1 RXNAK2=0 I2CRDY=1
BB=1 RXNAK2=1 I2CRDY=1
BB=0
Weltrend Semiconductor, Inc.
Page 28
WT6148/WT6160v1.02
Digital Monitor Controller
Slave I2C Data Sequence
(1) Write mode :
START MSCL MSDA
MSDA output
Pull low MSCL
Pull low MSCL
A
Pull low MSCL STOP
A
Slave Address
0A
RX DATA 1
RX DATA 2
A
A
A
I2CRDY
write REG#12H to release MSCL
BB=1 SFIRST=1 SSTOP=0 SRW=0 RXNAK2=0 I2CRDY=1
BB=1 SFIRST=0 SSTOP=0 SRW=0 RXNAK2=0 I2CRDY=1
BB=1 SFIRST=0 SSTOP=0 SRW=0 RXNAK2=0 I2CRDY=1
BB=1 SFIRST=0 SSTOP=1 SRW=0 RXNAK2=0 I2CRDY=1
(2) Read mode (I) :
START MSCL MSDA
MSDA output Pull low MSCL Pull low MSCL Pull low MSCL
STOP
Slave Address
1A
A
TX DATA 1 TX DATA 1
SET I2CRW
A
TX DATA 2 TX DATA 2
N
I2CRDY
write REG#12H to release MSCL
BB=1 SFIRST=1 SSTOP=0 SRW=1 RXNAK2=0 I2CRDY=1
BB=1 SFIRST=0 SSTOP=0 SRW=1 RXNAK2=0 I2CRDY=1
BB=1 SFIRST=0 SSTOP=0 SRW=1 RXNAK2=1 I2CRDY=1
BB=1 SFIRST=0 SSTOP=1 SRW=1 RXNAK2=1 I2CRDY=1
(3) Read mode (II) :
START MSCL MSDA
MSDA output Pull low MSCL Pull low MSCL Pull low MSCLSTOP
Slave Address
1A
RX DATA
A
A
A
TX DATA TX DATA
SET I2CRW
N
I2CRDY
write REG#12H to release MSCL
BB=1 SFIRST=1 SSTOP=0 SRW=1 RXNAK2=0 I2CRDY=1
BB=1 SFIRST=0 SSTOP=0 SRW=1 RXNAK2=0 I2CRDY=1
BB=1 SFIRST=0 SSTOP=0 SRW=1 RXNAK2=1 I2CRDY=1
BB=1 SFIRST=0 SSTOP=1 SRW=1 RXNAK2=1 I2CRDY=1
Weltrend Semiconductor, Inc.
Page 29
WT6148/WT6160v1.02
Digital Monitor Controller
I2C interface Status Register
Name Addr R/W Initial R 22h Bit 7 -Bit 6 -Bit 5 BB Bit4 SFIRST Bit 3 SSTOP Bit 2 SRW Bit 1 RXNAK2 Bit 0 I2CRDY I2C_STA 0010h
Bit Name BB SFIRST SSTOP SRW
Description "1" : Bus busy. "0" : Bus idle. Both SDA2 and SCL2 pins keep in high level for 5us after STOP condition. This bit is set when received START and first byte in slave mode. This bit is set when received STOP condition in slave mode. Received R/W bit in slave mode. "1" : Read command is received. "0" : Write command is received. "1" : NACK is received. "0" : ACK is received. This bit is set when a byte is received, transmitted or STOP condition is detected.
RXNAK2 I2CRDY
I2C interface Control Register
Name Addr R/W Initial W 02h Bit 7 ENI2C Bit 6 MCLK1 Bit 5 MCLK0 Bit4 MSTR Bit 3 MSTOP Bit 2 I2CRW Bit 1 TXNAK2 Bit 0 SLAVE I2C_CON 0010h
Bit Name ENI2C MCLK1,0
MSTR MSTOP I2CRW
TXNAK2 SLAVE
Description "1" : Enable I2C interface. "0" : Pin PB5 and pin PB4 are I/O port. Select SCL clock in master mode "00" : 400KHz "01" : 100KHz "11" : 200KHz "10" : 50KHz Output START condition in master mode when this bit is set. Output STOP condition in master mode when this bit is set. "0" : Transmitter , "1" : Receiver in master mode. "1" : Transmitter , "0" : Receiver in slave mode ("0" : I2C write mode, "1" : I2C read mode. ) "1" : Output NACK. "0" : Output ACK. It will pull low the SDA2 pin on acknowledge bit. "1" : Slave mode. "0" : Master mode.
I2C interface Transmit/Receive Buffer Register
Name I2C_TX I2C_RX Addr 0011h 0011h R/W Initial W R xxh xxh Bit 7 MTX7 MRX7 Bit 6 MTX6 MRX6 Bit 5 MTX5 MRX5 Bit4 MTX4 MRX4 Bit 3 MTX3 MRX3 Bit 2 MTX2 MRX2 Bit 1 MTX1 MRX1 Bit 0 MTX0 MRX0
I2C interface Address Register
Name Addr R/W Initial W xxh Bit 7 SAR7 Bit 6 SAR6 Bit 5 SAR5 Bit4 SAR4 Bit 3 SAR3 Bit 2 SAR2 Bit 1 SAR1 Bit 0 -I2C_ADR 0012h
Bit Name Description SAR7 ~ SAR1 7-bit address to be compared in slave mode.
Weltrend Semiconductor, Inc.
Page 30
WT6148/WT6160v1.02
Digital Monitor Controller Master I2C Flow Chart
START
set ENMI2C (W10.7) select MCLK,MCLK0W10.6,W10.5) (
BB(R10.5)=0?
Yes
No
time out ? clear I2CRW(W10.2) clear TXNAK2 (W10.1) send slave address =>MI2C_TX(W11) set MSTR (W10.4)
Yes
No
hardware fail
No
I2CRDY(R10.0)=1?
Yes
RXNAK2(R10.1)=0?
Yes
No
set MSTOP (W10.3) "XX"=>MI2C_AR(W12)
WRITE mode
READ mode
send data =>MI2C_TX(W11) "XX"=>MI2C_AR(W12)
set I2CRW(W10.2)
read last byte ? I2CRDY(R10.0)=1?
Yes No No
Yes
set TXNAK2 (W10.1) "XX"=>MI2C_AR(W12)
"XX"=>MI2C_AR(W12)
No
RXNAK2(R10.1)=0?
Yes
I2CRDY(R10.0)=1?
Yes Yes
No
No
I2CRDY(R10.0)=1?
Yes
all bytes sended ?
No
read MI2C_RX (R11) set MSTOP (W10.3) "XX"=>MI2C_AR(W12) send data =>MI2C_TX(W11) "XX"=>MI2C_AR(W12)
read MI2C_RX (R11) set MSTOP (W10.3) "XX"=>MI2C_AR(W12)
Weltrend Semiconductor, Inc.
Page 31
WT6148/WT6160v1.02
Digital Monitor Controller Master I2C (restart mode) Flow Chart
START
set ENMI2C (W10.7) select MCLK,MCLK0 (W10.6,W10.5)
BB(R10.5)=0?
Yes
No
clear I2CRW (W10.2) clear TXNAK2 (W10.1) send slave address =>MI2C_TX(W11) set MSTR (W10.4)
time out ?
Yes
No
hardware fail
No
I2CRDY(R10.0)=1?
Yes
No
RXNAK2(R10.1)=0?
Yes
send data =>MI2C_TX(W11) "XX"=>MI2C_AR(W12)
No
I2CRDY(R10.0)=1?
Yes
No
RXNAK2(R10.1)=0?
Yes
send slave address =>MI2C_TX(W11) set MSTR (W10.4) "XX"=>MI2C_AR(W12)
set I2CRW (W10.2)
read last byte ?
No
No
set TXNAK2 (W10.1) "XX"=>MI2C_AR(W12)
I2CRDY(R10.0)=1?
Yes
"XX"=>MI2C_AR(W12)
RXNAK2(R10.1)=0?
No
Yes
No
I2CRDY(R10.0)=1?
Yes
No
No
I2CRDY(R10.0)=1?
Yes
read MI2C_RX (R11) set MSTOP (W10.3) "XX"=>MI2C_AR(W12)
read MI2C_RX (R11) set MSTOP (W10.3) "XX"=>MI2C_AR(W12)
END
Weltrend Semiconductor, Inc.
Page 32
WT6148/WT6160v1.02
Digital Monitor Controller Slave I2C Flow Chart
START
setENMI2C (W10.7) slave address =>MI2C_AR(W12) set SLAVE(W10.0)
No
MI2CRDY(R10.0)=1?
Yes
SFIRST(R10.4)=1?
Yes
No
SSTOP (R10.3) =1?
No
No
SRW (R10.2) =1?
Yes
Yes
SRW(R10.2)=1? slave address=>MI2C_AR(W12)
Yes
No
set I2CRW(W10.2) send data => MI2C_TX(W11)
No
read MI2C_RX(R11)
RXNAK2R10.1) ( =0? slave address=>MI2C_AR(W12)
Yes
slave address=>MI2C_AR(W12)
send data => MI2C_TX(W11)
slave address=>MI2C_AR(W12)
Weltrend Semiconductor, Inc.
Page 33
WT6148/WT6160v1.02
Digital Monitor Controller Timer
It is a 6-bit down counter with 2-bit prescaler. The time base is selected by PS1 and PS0 bits. Timer starts counting when writing data to TIMER register. When the counter reaches zero, the counter stops and sets interrupt flag (IF_TMR). If program wants to start the timer again, write data to TIMER register.
PS1 PS0 0.256ms 0.512ms 1.024ms 4.096ms
TIM0 TIM1 TIM2 TIM3 TIM4 TIM5
Time base Selector
6-Bit Timer
IF_TMR
IE_TMR
Fig.11 Block diagram of Timer Timer Register
Name TIMER Addr 0018h R/W Initial W 00h Bit 7 PS1 Bit 6 PS0 Bit 5 TIM5 Bit4 TIM4 Bit 3 TIM3 Bit 2 TIM2 Bit 1 TIM1 Bit 0 TIM0
Prescaler of timer. "00" : time base = 0.256ms "01" : time base = 0.512ms "10" : time base = 1.024ms "11" : time base = 4.096ms TIM5 ~ TIM0 Timer period = time base x (6-bit data) + ( 0 --1 ) x time base
Bit Name PS1,PS0
Bit Description
Weltrend Semiconductor, Inc.
Page 34
WT6148/WT6160v1.02
Digital Monitor Controller A/D converter
The Analog-to-Digital Converter (ADC) has 6 -bit resolution with four selectable input channels. When EN_CHx is set, PCx is configured as ADC input and PCx pull-high resistor is disabled. When CHx is set, it will reset the ADC_DA register and start converting. After the conversion is done, the ADRDY bit is set and valid data is stored in AD5~AD0 bits. The total conversion time is from 512us to 1.024ms. If program want to make a new conversion, write CHx register again and it will start another conversion. ADC Data Register
Name Addr R/W Initial R 0xh Bit 7 ADRDY Bit 6 -Bit 5 AD5 Bit4 AD4 Bit 3 AD3 Bit 2 AD2 Bit 1 AD1 Bit 0 AD0 ADC_DA 001Ah
Bit Name ADRDY AD5 ~ AD0
Bit Description ADC data is ready to read when this bit is set. ADC data.
ADC Channel Select Register
Name Addr R/W Initial W 00h Bit 7 Bit 6 Bit 5 Bit4 Bit 3 CH3 Bit 2 CH2 Bit 1 CH1 Bit 0 CH0 ADC_CH 001Ah EN_CH3 EN_CH2 EN_CH1 EN_CH0
Bit Name EN_CH3 EN_CH2 EN_CH1 EN_CH0 CH3 CH2 CH1 CH0
Bit Description "1" : PC3 is configured as ADC interface. (Disable PC3 pull-high resistor). "0" : PC3 is configured as I/O port. "1" : PC2 is configured as ADC interface. (Disable PC2 pull-high resistor). "0" : PC2 is configured as I/O port. "1" : PC1 is configured as ADC interface. (Disable PC1 pull-high resistor). "0" : PC1 is configured as I/O port. "1" : PC0 is configured as ADC interface. (Disable PC0 pull-high resistor). "0" : PC0 is configured as I/O port. Select AD3 pin to ADC convert when this bit is set. Select AD2 pin to ADC convert when this bit is set. Select AD1 pin to ADC convert when this bit is set. Select AD0 pin to ADC convert when this bit is set.
Weltrend Semiconductor, Inc.
Page 35
WT6148/WT6160v1.02
Digital Monitor Controller
CH3 AD3 CH2 AD2 CH1 AD1 CH0 AD0 Resistor Array Comparator
6-bit Counter Fig.12 Block diagram of ADC
ADRDY
A/D Converter Flow Chart
START
set EN_CH3 (W1A.7) or EN_CH2(W1A.6) or EN_CH1(W1A.5) or EN_CH0(W1A.4)
set CH3 (W1A.3) or CH2(W1A.2) or CH1(W1A.1) or CH0(W1A.0)
No
ADRDY(R1A.7)=1 ?
Yes
read ADC_DA(R1A)
Weltrend Semiconductor, Inc.
Page 36
WT6148/WT6160v1.02
Digital Monitor Controller Interrupt Control
There are two interrupt vectors of CPU. The high priority interrupt INT0 (vector in $FFFAh and $FFFBh) is used for DDC interface interrupt. The low priority INT1 (vector in $FFFEh and $FFFFh) is ORed by six interrupt sources. Each interrupt can be enabled/disabled independently by programming INT_EN register and identified by INT_FLAG register. DDC interface interrupt Interrupt Condition Clear Interrupt Transmit data buffer is empty in DDC1 mode. Write data to DDC_RX register. A high to low transition on SCL1 pin in DDC1 Set CLRH2L bit in DDC_CON register and clear it . mode. Receive one byte in DDC2 mode. Write address to DDC_AR0 register. Transmit data buffer is empty in DDC2 mode. Write address to DDC_AR0 register. Received a STOP condition in DDC2 mode. Write address to DDC_AR0 register. I2C interface interrupt Interrupt Condition After transmit a byte. After receive a byte. Received a STOP condition.
Clear Interrupt Write address to MI2C_AR register. Write address to MI2C_AR register. Write address to MI2C_AR register.
Sync Processor interrupt Interrupt Condition Clear Interrupt Latch a new H frequency to HFREQ_H and Read HFREQ_H Register. HFREQ_L register every 32.768ms or 16.384ms. Timer interrupt Interrupt Condition Timer expired. IRQ pin interrupt Interrupt Condition Low level or falling edge on /IRQ pin. Vsync output interrupt Interrupt Condition Leading edge of VOUT pin signal. Vsync input interrupt Interrupt Condition Leading edge of VIN pin signal.
Clear Interrupt Write a value to TIMER register
Clear Interrupt Set CLR_IRQ bit in IRQ_CON register and clear it .
Clear Interrupt Set CLR_VSO bit in IRQ_CON register and clear it .
Clear Interrupt Set CLR_VIN bit in IRQ_CON register and clear it .
Interrupt Flag Register
Name Addr R/W Initial R 00h Bit 7 IF_DDC Bit 6 IF_MI2C Bit 5 -Bit4 IF_SYNC Bit 3 IF_TMR Bit 2 IF_IRQ Bit 1 IF_VSO Bit 0 IF_VIN INT_FLAG 001Bh
Weltrend Semiconductor, Inc.
Page 37
WT6148/WT6160v1.02
Digital Monitor Controller
Bit Name IF_DDC IF_MI2C IF_SYNC IF_TMR IF_IRQ IF_VSO IF_VIN Bit Description Indicate DDC interrupt when this bit is set. Indicate I2C interrupt when this bit is set. Indicate sync processor interrupt when this bit is set. Indicate Timer interrupt when this bit is set. Indicate IRQ interrupt when this bit is set. Indicate VOUT interrupt when this bit is set. Indicate VIN interrupt when this bit is set.
Interrupt Enable Register
Name INT_EN Addr R/W Initial 001Bh W 00h Bit 7 IE_DDC Bit 6 IE_MI2C Bit 5 -Bit4 Bit 3 Bit 2 IE_IRQ Bit 1 IE_VSO Bit 0 IE_VIN IE_SYNC IE_TMR
Bit Name IE_DDC IE_MI2C IE_SYNC IE_TMR IE_IRQ IE_VSO IE_VIN
Bit Description Enable DDC interrupt when this bit is set. Enable I2C interrupt when this bit is set. Enable sync processor interrupt when this bit is set. Enable Timer interrupt when this bit is set. Enable IRQ interrupt when this bit is set. Enable VOUT interrupt when this bit is set. Enable VIN interrupt when this bit is set.
Interrupt Source Register
Name INT_SRC Addr R/W Initial 001Ch R Bit 7 -Bit 6 -Bit 5 -Bit4 SYNC Bit 3 TIMER Bit 2 IRQ Bit 1 VSO Bit 0 VIN
Bit Name SYNC TIMER IRQ VSO VIN
Bit Description Indicate H frequency counter is ready to read when this bit is set.. Indicate Timer expired when this bit is set. Indicate a low level or falling edge occurs on IRQ pin when this bit is set. Indicate a leading edge occurs on VOUT pin when this bit is set. Indicate a leading edge occurs on VIN pin when this bit is set.
IRQ Control Register
Name Addr R/W Initial 00h Bit 7 -Bit 6 -Bit 5 -Bit4 -Bit 3
CLR_VIN
Bit 2
Bit 1
Bit 0
IRQ_CON 001Ch W
CLR_IRQ CLR_VSO IRQ_EG
Bit Name CLR_IRQ CLR_VSO CLR_VIN IRQ_EG
Bit Description Clear IRQ interrupt when this bit is set. Clear VOUT interrupt when this bit is set. Clear Vsync input interrupt when this bit is set. Select IRQ pin interrupt type. "1" : Falling edge "0" : Low level
Weltrend Semiconductor, Inc.
Page 38
WT6148/WT6160v1.02
Digital Monitor Controller Watchdog Timer
Watchdog timer will generate a reset pulse if CPU does not write WDT register within 259.072ms or 518.144ms. This function can be disabling by setting DISWDT bit. Watchdog Timer Register
Name WDT Addr 001Dh R/W Initial W 00h Bit 7 -Bit 6 -Bit 5 -Bit4 -Bit 3 -Bit 2 -Bit 1 DISWDT Bit 0 WDT
Bit Name DISWDT WDT
Description "1" : Disable Watchdog Timer. "0" : Enable Watchdog Timer. "1" : Watchdog Timer reset period is 518.144ms +8.096ms. "0" : Watchdog Timer reset period is 259.072ms +8.096ms.
Function Configuration Register
This register controls the special configuration of WT6148/ WT6160.
Name Addr R/W Initial W 00h Bit 7 Bit 6 -Bit 5 -Bit4 -Bit 3 DISRST Bit 2 STEST Bit 1 Bit 0
OPTION 0FFFh
Bit Name STEST DISRST
Bit Value = "1" For IC test only. Do not set this bit. Disable illegal address reset.
Bit Value = "0" For normal operation. Enable illegal address reset.
Weltrend Semiconductor, Inc.
Page 39
WT6148/WT6160v1.02
Digital Monitor Controller PWM
There are 14 PWMs provided. PWM0 ~ PWM1 : +5V open-drain output. PWM2 ~ PWM3 : +10V open-drain output. PWM4 ~ PWM7 : +5V open-drain output, shared with I/O port D. PWM8 ~ PWM13 : +5V push-pull output, shared with I/O port A. The corresponding PWM register controls the PWM duty cycle. Duty cycle range is from 0/256 to 255/256. LSB 3-bit of PWM register determines which frame will be extended two Tosc. ( Tosc = 1/12MHz) 000 : no extended pulse. 001 : extend two Tosc in frame 4. 010 : extended two Tosc in frame 2 and 6. 011 : extended two Tosc in frame 2, 4 and 6. 100 : extended two Tosc in frame 1, 3, 5 and 7. 101 : extended two Tosc in frame 1, 3, 4, 5 and 7. 110 : extended two Tosc in frame 1, 2, 3, 5, 6 and 7. 111 : extended two Tosc in frame 1, 2, 3, 4, 5, 6 and 7. MSB 5-bit of PWM register determines 0/32 to 31/32 duty cycle in each frame. Frame 0 PWM=00001000 2 Tosc 2 Tosc PWM=00001001 2 Tosc 2 Tosc 2 Tosc 4 Tosc 2 Tosc 2 Tosc 2 Tosc Frame 1 Frame 2 Frame 3 Frame 4 Frame 5 Frame 6 Frame 7
64 Tosc 4 Tosc PWM=00010010 4 Tosc 6 Tosc 4 Tosc 4 Tosc 4 Tosc 6 Tosc 4 Tosc
512 Tosc
Fig. 13 PWM output waveform
Weltrend Semiconductor, Inc.
Page 40
WT6148/WT6160v1.02
Digital Monitor Controller PWM Registers
Name PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 PWM8 PWM9 PWM10 PWM11 PWM12 PWM13 PWM_EN1 PWM_EN2 Addr R/W Initial 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W W 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 80h 00h 00h Bit 7 PWM0 7 PWM1 7 PWM2 7 PWM3 7 PWM4 7 PWM5 7 PWM6 7 PWM7 7 PWM8 7 PWM9 7 PWM107 PWM117 PWM127 PWM137 --Bit 6 PWM0 6 PWM1 6 PWM26 PWM3 6 PWM4 6 PWM5 6 PWM6 6 PWM7 6 PWM8 6 PWM9 6 PWM106 PWM116 PWM126 PWM136 --Bit 5 PWM0 5 PWM1 5 PWM2 5 PWM3 5 PWM4 5 PWM5 5 PWM6 5 PWM7 5 PWM8 5 PWM9 5 PWM105 PWM115 PWM125 PWM135 -EPWM13 Bit4 PWM0 4 PWM1 4 PWM2 4 PWM3 4 PWM4 4 PWM5 4 PWM6 4 PWM7 4 PWM8 4 PWM9 4 PWM104 PWM114 PWM124 PWM134 -EPWM12 Bit 3 PWM0 3 PWM1 3 PWM2 3 PWM3 3 PWM4 3 PWM5 3 PWM6 3 PWM7 3 PWM8 3 PWM9 3 PWM103 PWM113 PWM123 PWM133 EPWM7 EPWM11 Bit 2 PWM0 2 PWM1 2 PWM2 2 PWM3 2 PWM4 2 PWM5 2 PWM6 2 PWM7 2 PWM8 2 PWM9 2 PWM102 PWM112 PWM122 PWM132 EPWM6 EPWM10 Bit 1 PWM0 1 PWM1 1 PWM2 1 PWM3 1 PWM4 1 PWM5 1 PWM6 1 PWM7 1 PWM8 1 PWM9 1 PWM101 PWM111 PWM121 PWM131 EPWM5 EPWM9 Bit 0 PWM0 0 PWM1 0 PWM2 0 PWM3 0 PWM4 0 PWM5 0 PWM6 0 PWM7 0 PWM8 0 PWM90 PWM100 PWM110 PWM120 PWM130 EPWM4 EPWM8
Bit Name Description PWMX 7 ~ PWMX 0 Select duty cycle of PWM output. 00000000 : duty cycle = 0 00000001 : duty cycle = 1/256 00000010 : duty cycle = 2/256 : 11111110 : duty cycle = 254/256 11111111 : duty cycle = 255/256 EPWMx Enable corresponding PWM output. ( x from 4 to 13) when it is set.
Weltrend Semiconductor, Inc.
Page 41
WT6148/WT6160v1.02
Digital Monitor Controller
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Min. Max. DC Supply Voltage (VDD) -0.3 7.0 Input and output voltage with respect to Ground -0.3 VDD+0.3 Storage temperature -25 125 Ambient temperature with power applied -10 85 *Note: Stresses above those listed may cause permanent damage to the devices Units V V o C o C
D.C Characteristics (VDD=5.0V5%, Ta=0-70C)
Symbol Parameter VDD Supply Voltage VIH VIL VIH,SYNC VIL,SYNC VIH,RES VIL,RES VOH VOL Input High Voltage Input Low Voltage Sync Input High Voltage (Schmitt trigger) Sync Input Low Voltage (Schmitt trigger) Reset Input High Voltage (Schmitt trigger) Reset Input Low Voltage (Schmitt trigger) Output High Voltage Output Low Voltage PORT C Output Low Voltage PWM0,PWM1,PWM2,PWM3 Output Low Voltage Input Leakage Current HSYNC and VSYNC pins Pull High Resistance Operating Current Low VDD Reset Voltage Condition Min. 4.5 0.7VDD -0.3 2 -0.3 2 -0.3 IOH = -6mA IOL = 6mA IOL = 10mA IOL = 10mA 0V IIL,SYNC RPH IDD VRESET
FOSC= 12MHz, No load 3.6
Weltrend Semiconductor, Inc.
Page 42
WT6148/WT6160v1.02
Digital Monitor Controller A.C Characteristics (VDD=5.0V5%, fosc=12MHz, Ta=0-70C)
/RESET and /IRQ Timing
Symbol tLOW,RES tLOW,IRQ RESET IRQ tLOW,RES tHIGH,IRQ Parameter /RESET pin low pulse /IRQ low pulse (level trigger) Min. 167 167 Typ. Max. Units ns ns
SYNC Processor Timing
Symbol tHIGH,SYNC tLOW,SYNC HSYNC VSYNC tHIGH,SYNC tLOW,SYNC Parameter HSYNC and VSYNC high time HSYNC and VSYNC low time Min. 167 167 Typ. Max. Units ns ns
DDC1 Timing
Symbol tVAA,DDC1 Parameter SDA1 output valid from VSYNC rising edge Min. 125 Typ. Max. 500 Units ns
tVAA,DDC1 SDA1 Bit 0 (LSB) Null Bit Bit 7 (MSB)
VSYNC tHIGH,SYNC tLOW,SYNC
Weltrend Semiconductor, Inc.
Page 43
WT6148/WT6160v1.02
Digital Monitor Controller
DDC2B Timing
Symbol fSCL tBF tHD,START tSU,START tHIGH,SCL tLOW,SCL tHD,DATA tSU,DATA tRISE,DDC tFALL.DDC tSU,STOP Parameter SCL1 input clock frequency Bus free time Hold time for START condition Set-up time for START condition SCL1 clock high time SCL1 clock low time Hold time for DATA input Hold time for DATA output Set-up time for DATA input Set-up time for DATA output SCL1 and SDA1 rise time SCL1 and SDA1 fall time Set-up time for STOP condition Min. 0 2 1 1 1 1 0 167 167 334 2 Typ. Max. 100 1 300 Units kHz us us us us us ns ns ns ns us ns us
tBF SDA1 tHD,START SCL1 tSU,STOP tLOW,SCL tHD,DATA tHIGH,SCL tSU,DATA tSU,START tRISE tFALL
Weltrend Semiconductor, Inc.
Page 44
WT6148/WT6160v1.02
Digital Monitor Controller TYPICAL APPLICATION CIRCUIT
Reset Pin and Crystal Oscillator
PWM Output
Weltrend Semiconductor, Inc.
Page 45
WT6148/WT6160v1.02
Digital Monitor Controller
Hsync, Vsync and DDC Interface Protection
+5V
WT61xx
220 VIN HIN 220 100P 470P 5.1V
47K
47K VSYNC HSYNC
+5V
47K 150 SCL1 SDA1 150 5.1V
10K SCL SDA
The resistors, capacitors and circuit are reference only.
Weltrend Semiconductor, Inc.
Page 46

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